All of the read-cycle phases mentioned previously should have a duration that is predefined and compatible with the memory-access times provided by the specifics of the memory circuit.
All the various phases of the read cycle are scanned by synchronization pulses deriving from a single main pulse called ATD (address transition detection). The ATD pulse is generated within the memory circuit whenever a change in the address is detected at its input terminals.
Generation of the ATD pulse is generally requested by a logical NOR network, which normally has an output at the high logic level.
When a change in the logic level occurs, even on only one of the input terminals, the logical NOR network changes the output itself, permitting a terminal that has been sampled by the ATD pulse to discharge to ground.
In reality, there are many logical networks that permit realization of an ATD pulse generating circuit.
A first example of such an ATD pulse generating circuit includes the use of transistors of the CMOS type. In this case, very complex logic networks are obtained, and, given the high number of addresses to be detected that are normally contained in a memory, a tree organization of the network used is made necessary, i.e., a structure including many levels.
Logical networks made in this way are called "full CMOS" in technical language, and they permit the generation of very narrow and rapid ATD pulses.
However, the principal disadvantage of full-CMOS networks consists of the presence of intrinsic delays due to the various logic levels of the tree structure used and to the consistent obstacles arising from the complexity of the network itself, for example from the presence of PMOS and NMOS transistors at every point monitored by all the subsequent level structures.
Alternatively, it is possible to realize an ATD pulse generating circuit by means of MOS transistors with an N channel, or NMOS. Networks simpler than full-CMOS networks are obtained in this manner, which are called "NMOS" networks and are arranged basically according to an OR configuration using a single pull-up transistor.
Such a pull-up transistor has only one control-gate terminal connected to a ground voltage reference, and therefore a higher resistance to guarantee a low threshold level for switching on the transistor that is less than a Vtp value equal to the threshold voltage of a PMOS transistor, even in the presence of high voltages. The ATD pulse line obtained in this manner is detected in the very capacitative realizations that produce rapid ATD pulses on a first switching leading edge of an input signal but very slow on a second switching leading edge. This slowness is caused by the charge resistivity and the capacitance of the line.
In particular, this second switching leading edge turns out to be strongly dependent on the process parameters, on the operating conditions, on the operating temperature, and on the entire context of operation of the network. Disadvantageously, however, an ATD signal of a non-pulse type is obtained by means of such "NMOS" networks, depending on the parameters of the network. Moreover, "NMOS" networks also absorb current as they operate, because of the presence of the resistive pull-up transistor.
It is possible to obtain, starting from an "NMOS" network, an ATD pulse generating circuit with much faster dynamics, that is, with rapid switching on both its leading edges, but with the addition of particular consolidations that increase the complexity of the network.